Organic light emitting display device

ABSTRACT

An organic light emitting display device includes a substrate, a light emitting diode, a first transistor controlling a driving current of the light emitting diode, a second transistor including a second drain electrode connected to a first source electrode of the first transistor, a second gate electrode, a second channel overlapped with the second gate electrode when viewed in a plan view, a second source electrode facing the second drain electrode with the second channel interposed therebetween, and a lower gate electrode, and a plurality of driving voltage lines transmitting a first driving voltage. The lower gate electrode of the second transistor is overlapped with the second channel when viewed in a plan view, and the lower gate electrode is electrically connected to a corresponding driving voltage line among the driving voltage lines.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application is a continuationapplication of U.S. patent application Ser. No. 16/434,237 filed on Jun.7, 2019, which claims priority under 35 USC § 119 to Korean PatentApplication No. 10-2018-0101369, filed on Aug. 28, 2018, in the KoreanIntellectual Property Office, the disclosures of which are incorporatedherein in their entirety by reference.

BACKGROUND 1. Field of Disclosure

The present disclosure relates to a display device. More particularly,the present disclosure relates to an organic light emitting displaydevice including the pixel.

2. Description of the Related Art

An organic light emitting display device includes pixels. Each of thepixels includes an organic light emitting diode and a circuit partcontrolling the organic light emitting diode. The circuit part includesat least a switching transistor, a driving transistor, and a storagecapacitor.

The organic light emitting diode includes an anode, a cathode, and anorganic light emitting layer disposed between the anode and the cathode.The organic light emitting diode emits a light when a voltage equal toor greater than a threshold voltage of the organic light emitting layeris applied to between the anode and the cathode.

SUMMARY

The present disclosure provides an organic light emitting display deviceincluding the pixel.

Embodiments of the inventive concept provide an organic light emittingdisplay device including a substrate, a light emitting diode disposed onthe substrate and including an anode and a cathode, a first transistorincluding a first source electrode, a first gate electrode, a firstchannel overlapped with the first gate electrode when viewed in a planview, and a first drain electrode facing the first source electrode withthe first channel interposed therebetween and controlling a drivingcurrent of the light emitting diode, a second transistor including asecond drain electrode connected to the first source electrode of thefirst transistor, a second gate electrode, a second channel overlappedwith the second gate electrode when viewed in a plan view, a secondsource electrode facing the second drain electrode with the secondchannel interposed therebetween and a lower gate electrode, and aplurality of driving voltage lines transmitting a first driving voltage.The lower gate electrode of the second transistor is overlapped with thesecond channel when viewed in a plan view, and the lower gate electrodeis electrically connected to a corresponding driving voltage line amongthe driving voltage lines.

The organic light emitting display device further includes a pluralityof scan lines extending in a first direction and arranged spaced apartfrom each other in a second direction crossing the first direction, andthe second gate electrode of the second transistor is connected to acorresponding scan line among the scan lines.

The driving voltage lines respectively correspond to the scan lines andeach of the driving voltage lines is overlapped with a correspondingscan line among the scan lines.

The driving voltage lines are electrically connected to each other.

A width in the second direction of each of the driving voltage lines iswider than a width in the second direction of the corresponding scanline among the scan lines.

The organic light emitting display device further includes a voltageline extending in the second direction in the non-display area, thesubstrate includes a display area in which the light emitting diode isdisposed and a non-display area disposed adjacent to the display area,and the driving voltage lines extend from the voltage line in the firstdirection.

The lower gate electrode is disposed between the substrate and a secondactive pattern that includes the second source electrode, the secondchannel, and the second drain electrode of the second transistor.

The driving voltage lines is not overlapped with a first active patternthat includes the first source electrode, the first channel, and thefirst drain electrode of the first transistor when viewed in a planview.

The organic light emitting display device further includes a pluralityof data lines extending in a second direction and arranged spaced apartfrom each other in a first direction different from the seconddirection, and the second source electrode of the second transistor isconnected to a corresponding data line among the data lines.

The driving voltage lines respectively correspond to the data lines andeach of the driving voltage lines is overlapped with the correspondingdata line among the data lines.

The driving voltage lines are connected to each other.

Each of the driving voltage lines has a width wider than a width in thefirst direction of the corresponding data line among the data lines.

A doping concentration of the first channel of the first transistor isdifferent from a doping concentration of the second channel of thesecond transistor.

The organic light emitting display device further includes a sixthtransistor that comprises a sixth source electrode connected to thefirst drain electrode of the first transistor, a sixth drain electrodeconnected to the anode of the light emitting diode, and a sixth channeldisposed between the sixth source electrode and the sixth drainelectrode.

Embodiments of the inventive concept provide an organic light emittingdisplay device including a substrate, a plurality of pixels disposed onthe substrate, a plurality of scan lines extending in a first directionand respectively connected to the pixels, a plurality of data linesextending in a second direction crossing the first direction andrespectively connected to the pixels, and a plurality of driving voltagelines transmitting a first driving voltage to the pixels. Each of thepixels includes a light emitting diode that includes an anode and acathode, a first transistor including a first source electrode, a firstgate electrode, a first channel overlapped with the first gate electrodewhen viewed in a plan view, and a first drain electrode facing the firstsource electrode with the first channel interposed therebetween andcontrolling a driving current of the light emitting diode, and a secondtransistor including a second drain electrode connected to the firstsource electrode of the first transistor, a second gate electrodeconnected to a corresponding scan line among the scan lines, a secondchannel overlapped with the second gate electrode when viewed in a planview, a second source electrode facing the second drain electrode withthe second channel interposed therebetween and connected to acorresponding data line among the data lines and a lower gate electrode.The lower gate electrode is electrically connected to a correspondingdriving voltage line among the driving voltage lines.

The lower gate electrode of the second transistor is overlapped with thesecond channel when viewed in a plan view.

The driving voltage lines extend in the first direction and each of thedriving voltage lines is overlapped with a corresponding scan line amongthe scan lines.

The organic light emitting display device further includes a voltageline extending in the second direction in the non-display area, thesubstrate includes a display area in which the light emitting diode isdisposed and a non-display area disposed adjacent to the display area,and the driving voltage lines extend from the voltage line in the firstdirection.

The driving voltage lines extend in the second direction, and each ofthe driving voltage line is overlapped with the corresponding data lineamong the data lines when viewed in a plan view.

The driving voltage lines are not overlapped with a first active patternthat includes the first source electrode, the first channel and thefirst drain electrode of the first transistor when viewed in a planview.

According to the above, the switching transistor of the organic lightemitting display device may have a double-gate structure, and a highvoltage may be applied to the lower gate electrode. Accordingly, thethreshold voltage of the switching transistor may be prevented frombeing positive shifted on a high-temperature operation environment, andthus a display quality may be improved. In addition, since the dopingconcentration of the active area of the switching transistor iscontrolled, a variation in range of the threshold voltage of theswitching transistor may be controlled. Therefore, the threshold voltageof the switching transistor may be finely controlled within a desiredrange by controlling the voltage applied to the lower gate electrode ofthe switching transistor and the doping concentration of the active areaof the switching transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other advantages of the present disclosure will becomereadily apparent by reference to the following detailed description whenconsidered in conjunction with the accompanying drawings wherein:

FIG. 1 is a block diagram showing an organic light emitting displaydevice according to an exemplary embodiment of the present disclosure;

FIG. 2 is an equivalent circuit diagram showing a pixel of an organiclight emitting display device according to an exemplary embodiment ofthe present disclosure;

FIG. 3 is a waveform diagram showing driving signals used to drive thepixel shown in FIG. 2;

FIG. 4 is a plan view showing one pixel of an organic light emittingdisplay device according to an exemplary embodiment of the presentdisclosure;

FIG. 5 is a cross-sectional view taken along a line VI-VI′ of FIG. 4 toshow the organic light emitting display device;

FIG. 6 is a view showing a variation of a threshold voltage of a secondtransistor shown in FIG. 2;

FIG. 7 is a plan view showing an AR1 area of the organic light emittingdisplay device shown in FIG. 1;

FIG. 8 is a cross-sectional view taken along a line VII-VII′ of FIG. 7;

FIGS. 9A, 9B, 9C, 9D, 9E and 9F are cross-sectional views taken alonglines VIII-VIII′ and IX-IX′ of FIG. 4;

FIG. 10 is a plan view showing an organic light emitting display deviceaccording to another exemplary embodiment of the present disclosure;

FIG. 11 is a plan view showing one pixel of an organic light emittingdisplay device according to an exemplary embodiment of the presentdisclosure; and

FIG. 12 is a cross-sectional view taken along a line X-X′ of FIG. 11 toshow the organic light emitting display device.

DETAILED DESCRIPTION

It will be understood that when an element or layer is referred to asbeing “on”, “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present.

Like numerals refer to like elements throughout. In the drawings, thethickness of layers, films, and regions are exaggerated for clarity.

As used herein, the term “and/or” includes any and all combinations ofone or more of the associated listed items.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, components, regions, layersand/or sections, these elements, components, regions, layers and/orsections should not be limited by these terms. These terms are only usedto distinguish one element, component, region, layer or section fromanother region, layer or section. Thus, a first element, component,region, layer or section discussed below could be termed a secondelement, component, region, layer or section without departing from theteachings of the present inventive concept. As used herein, the singularforms, “a”, “an” and “the” are intended to include the plural forms aswell, unless the context clearly indicates otherwise.

Spatially relative terms, such as “beneath”, “below”, “lower”, “above”,“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this inventive concept belongs. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

It will be further understood that the terms “includes” and/or“including”, when used in this specification, specify the presence ofstated features, integers, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, integers, steps, operations, elements, components,and/or groups thereof.

Hereinafter, the present inventive concept will be explained in detailwith reference to the accompanying drawings.

FIG. 1 is a block diagram showing an organic light emitting displaydevice according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1, the organic light emitting display device includesa display substrate 100, a timing controller 200, a scan driving circuit300, a data driving circuit 400, and a voltage generator 500.

The timing controller 200 receives input image signals (not shown) andconverts a data format of the input image signals to a data formatappropriate to an interface with the data driving circuit 400 togenerate image data RGB. The timing controller 200 outputs a scancontrol signal SCS, the image data RGB, and a data control signal DCS.

The scan driving circuit 300 receives the scan control signal SCS fromthe timing controller 200. The scan control signal SCS includes avertical start signal that starts an operation of the scan drivingcircuit 300 and a clock signal that determines an output timing ofsignals. The scan driving circuit 300 generates a plurality of scansignals and sequentially outputs the scan signals to a plurality of scanlines SL1 to SLn described later. In addition, the scan driving circuit300 generates a plurality of light emitting control signals in responseto the scan control signal SCS and outputs the light emitting controlsignals to a plurality of light emitting lines EL1 to ELn describedlater.

FIG. 1 shows the scan signals and the light emitting control signals,which are output from one scan driving circuit 300, however the presentdisclosure should not be limited thereto or thereby. According toanother embodiment, a plurality of scan driving circuits may output thescan signals after dividing the scan signals and may output the lightemitting control signals after dividing the light emitting controlsignals. In addition, according to another embodiment, a driving circuitthat generates and outputs the scan signals may be distinct from adriving circuit that generates and outputs the light emitting controlsignals.

The data driving circuit 400 receives the data control signal DCS andthe image data RGB from the timing controller 200. The data drivingcircuit 400 converts the image data RGB to data signals and outputs thedata signals to a plurality of data lines DL1 to DLm described later.The data signals are analog voltages corresponding to grayscale valuesof the image data RGB.

The voltage generator 500 generates voltages required for the operationof the organic light emitting display device. In the present exemplaryembodiment, the voltage generator 500 generates a first driving voltageELVDD, a second driving voltage ELVSS, an initialization voltage Vint,and a third driving voltage VGH. The third driving voltage VGH isapplied to a voltage line 510 arranged in a non-display area NDA of thedisplay substrate 100. The third driving voltage VGH may have a voltagelevel corresponding to a high voltage of the scan signals generated bythe scan driving circuit 300. According to another embodiment, the thirddriving voltage VGH may be applied to the scan driving circuit 300.

The display substrate 100 includes the scan lines SL1 to SLn, the lightemitting lines EL1 to ELn, the data lines DL1 to DLm, third drivingvoltage lines BML1 to BMLn, and pixels PX. The scan lines SL1 to SLnextend in a first direction DR1 and are arranged in a second directionDR2 to be spaced apart from each other.

Each of the light emitting lines EL1 to ELn may be arranged parallel toa corresponding scan line among the scan lines SL1 to SLn. In addition,each of the third driving voltage lines BML1 to BMLn may be arrangedparallel to a corresponding scan line among the scan lines SL1 to SLn.In the present exemplary embodiment, the number of the third drivingvoltage lines BML1 to BMLn is equal to the number of the pixels arrangedin the second direction DR2, i.e., the number of the scan lines SL1 toSLn. The data lines DL1 to DLm are insulated from the scan lines SL1 toSLn while crossing the scan lines SL1 to SLn.

Each of the pixels PX is connected to a corresponding scan line amongthe scan lines SL1 to SLn, a corresponding light emitting line among thelight emitting lines EL1 to ELn, and a corresponding data line among thedata lines DL1 to DLm. In addition, each of the pixels PX is connectedto a corresponding third driving voltage line among the third drivingvoltage lines BML1 to BMLn.

Each of the pixels PX receives a first driving voltage ELVDD, a seconddriving voltage ELVSS having a level lower than that of the firstdriving voltage ELVDD, and a third driving voltage VGH. Each of thepixels PX is connected to a first driving voltage line PL to which thefirst driving voltage ELVDD is applied. Each of the pixels PX isconnected to an initialization line RL receiving the initializationvoltage Vint.

Each of the pixels PX may be electrically connected to three scan lines.As shown in FIG. 1, pixels arranged in a second pixel row may beconnected to first, second, and third scan lines SL1, SL2, and SL3.

Although not shown in figures, the display substrate 100 may furtherinclude a plurality of dummy scan lines. The display substrate 100 mayfurther include a dummy scan line connected to pixels PX arranged in afirst pixel row and a dummy scan line connected to pixels PX arranged inan n-th pixel row. In addition, pixels (hereinafter, referred to as“pixels of a pixel column”) connected to one data line among the datalines DL1 to DLm may be connected to each other. Further, two adjacentpixels among the pixels of the pixel column may be electricallyconnected to each other.

Each of the pixels PX includes an organic light emitting diode (notshown) and a pixel circuit part (not shown) controlling the lightemission of the light emitting diode. The pixel circuit part includes aplurality of transistors and a capacitor. At least one of the scandriving circuit 300 and the data driving circuit 400 may includetransistors formed through the same process as the pixel circuit part.

The scan lines SL1 to SLn, the light emitting lines EL1 to ELn, thethird driving voltage lines BML1 to BMLn, the data lines DL1 to DLm, thefirst driving voltage line PL, the initialization line RL, the pixelsPX, the scan driving circuit 300, and the data driving circuit 400 maybe formed on the base substrate (not shown) through a plurality ofphotolithography processes. Insulating layers may be formed on the basesubstrate (not shown) through a plurality of depositing processes and aplurality of coating processes. Each of the insulating layers may be athin film layer that covers the entire of the display substrate 100 ormay include at least one insulating pattern overlapped with only aspecific component of the display substrate 100. The insulating layersinclude an organic layer and/or an inorganic layer. In addition, anencapsulation layer (not shown) may be further formed on the basesubstrate.

The display substrate 100 receives the first driving voltage ELVDD andthe second driving voltage ELVSS. The first driving voltage ELVDD may beapplied to the pixels PX through the first driving voltage line PL. Thesecond driving voltage ELVSS may be applied to the pixels PX throughelectrodes (not shown) formed on the display substrate 100 or a powersource line (not shown).

The display substrate 100 receives the initialization voltage Vint. Theinitialization voltage Vint may be applied to the pixels PX through theinitialization voltage line RL.

The display substrate 100 receives the third driving voltage VGH. Thethird driving voltage VGH may be applied to the pixels PX through thethird driving voltage lines BML1 to BMLn formed on the display panel.

The display substrate 100 includes a display area DPA and a non-displayarea NDA. The pixels PX are arranged in the display area DPA. In thepresent exemplary embodiment, the scan driving circuit 300 is disposedin the non-display area NDA disposed at one side of the display areaDPA. The third driving voltage VGH provided from the voltage generator500 is applied to the pixels PX through the voltage line 510 arranged inthe non-display area NDA and the third driving voltage lines BML1 toBMLn arranged in the display area DPA.

FIG. 2 is an equivalent circuit diagram showing a pixel of an organiclight emitting display device according to an exemplary embodiment ofthe present disclosure. FIG. 3 is a waveform diagram showing drivingsignals used to drive the pixel shown in FIG. 2.

FIG. 2 shows an equivalent circuit of an i-th data lines 171 among thedata lines DL1 to DLm, a j-th scan line 151 among the scan lines SL1 toSLn, a j-th light emitting control line 153 among the light emittinglines EL1 to ELn, and a pixel PXij connected to a j-th driving voltageline BMLj among the driving voltage lines BML1 to BMLn as arepresentative example. Each of the pixels PX shown in FIG. 1 may havethe same circuit configuration as the equivalent circuit of the pixelPXij shown in FIG. 2. In the present exemplary embodiment, the circuitpart of the pixel PXij includes seven transistors T1 to T7 and onecapacitor Cst. In addition, the first to seventh transistors T1 to T7may be a p-channel type transistor such as PMOS, however they should notbe limited thereto or thereby. That is, at least one of the first toseventh transistors T1 to T7 may be an n-channel type transistor. Inaddition, the configuration of the pixel according to the presentdisclosure should not be limited to that shown in FIG. 2. The circuitpart shown in FIG. 2 is merely exemplary, and the configuration of thecircuit part may vary.

Referring to FIG. 2, the pixel PXij according to the exemplaryembodiment includes signal lines 151, 152, 153, 154, 171, PL, and BMLj.The pixel PXij includes the first to seventh transistors T1, T2, T3, T4,T5, T6, and T7 connected to the signal lines 151, 152, 153, 154, 171,PL, and BMLj, the capacitor Cst, and at least one light emitting diodeED. In the present exemplary embodiment, one pixel PXij including onelight emitting diode ED will be described as a representative example.

The signal lines 151, 152, 153, 154, 171, PL and BMLj may include thescan lines 151, 152, and 154, the light emitting control line 153, thedata line 171, the first driving voltage line PL, and the third drivingvoltage line BMLj.

The scan lines 151, 152, and 154 may transmit scan signals GWj, GIj andGBj, respectively. The scan signals GWj, GIj and GBj may transmit agate-on voltage and a gate-off voltage to turn on or off the transistorsT2, T3, T4, and T7 included in the pixel PXij.

The scan lines 151, 152 and 154 connected to the pixel PXij may includea first scan line 151 that transmits the scan signal GWj, a second scanline 152 that transmits the scan signal GIj having the gate-on voltageat a different timing from the first scan line 151, and a third scanline 154 that transmits the scan signal GBj. In the present exemplaryembodiment, an example in which the second scan line 152 transmits thegate-on voltage at a timing faster than the first scan line 151 will bemainly described. For example, in a case where the scan signal GWj is aj-th scan signal Sj (j is a natural number equal to or greater than 1)among the scan signals applied during one frame period, the scan signalGIj may be a previous scan signal such as a (j−1)th scan signal S(j−1),and the scan signal GBj may be a (j+1)th scan signal S(j+1), however thepresent disclosure should not be limited thereto or thereby. That is,the scan signal GBj may be a scan signal rather than the (j+1)th scansignal S(j+1).

The light emitting control line 153 may transmit the control signal andparticularly may transmit the light emitting control signal used tocontrol the light emission of the light emitting diode ED included inthe pixel PXij. The light emitting control signal transmitted throughthe light emitting control line 153 may have a different waveform fromthe scan signals transmitted through the scan lines 151, 152, and 154.The data line 171 transmits the data signal Di, and the first drivingvoltage line PL transmits the first driving voltage ELVDD. The datasignal Di may have a voltage level varied depending on the image signalinput to the display device, and the first driving voltage ELVDD mayhave a substantially constant level.

The first scan line 151 may transmit the scan signal GWj to the secondtransistor T2 and the third transistor T3, the second scan line 152 maytransmit the scan signal GIj to the fourth transistor T4, the third scanline 154 may transmit the scan signal GBj to the seventh transistor T7,and the light emitting control line 153 may transmit the light emittingcontrol signal Ej to the fifth transistor T5 and the sixth transistorT6.

A first gate electrode G1 of the first transistor T1 is connected to oneend of the capacitor Cst, a first source electrode S1 of the firsttransistor T1 is connected to the first driving voltage line PL via thefifth transistor T5, and a first drain electrode D1 of the firsttransistor T1 is electrically connected to an anode of the lightemitting diode ED via the sixth transistor T6. The first transistor T1receives the data signal Di transmitted through the data line 171 inresponse to a switching operation of the second transistor T2 andsupplies a driving current Id to the light emitting diode ED.

A second gate electrode G2 of the second transistor T2 is connected tothe first scan line 151, a second source electrode S2 of the secondtransistor T2 is connected to the data line 171, and a second drainelectrode D2 of the second transistor T2 is connected to the sourceelectrode S1 of the first transistor T1 and to the first driving voltageline PL through the fifth transistor T5. The second transistor T2 isturned on in response to the scan signal GWj applied thereto through thefirst scan line 151 and transmits the data signal Di provided throughthe data line 171 to the source electrode S1 of the first transistor T1.

In the present exemplary embodiment, the second transistor T2 has a dualgate structure including a lower gate electrode BG2 in addition to thegate electrode G2. The lower gate electrode BG2 of the second transistorT2 is connected to the third driving voltage line BMLj.

A third gate electrode G3 of the third transistor T3 is connected to thefirst scan line 151. A third drain electrode D3 of the third transistorT3 is commonly connected to a drain electrode D4 of the fourthtransistor T4, the one end of the capacitor Cst, and the first gateelectrode G1 of the first transistor T1. A third source electrode S3 ofthe third transistor T3 is connected to the drain electrode D1 of thefirst transistor T1 and to the anode of the light emitting diode EDthrough the sixth transistor T6.

The third transistor T3 is turned on in response to the scan signal GWjapplied thereto through the first scan line 151 to connect the firstgate electrode G1 and the drain electrode D1 of the first transistor T1,and thus the first transistor T1 is connected in a diode configuration.

A fourth gate electrode G4 of the fourth transistor T4 is connected tothe second scan line 152, a fourth source electrode S4 of the fourthtransistor T4 is connected to the initialization voltage line RLtransmitting the initialization voltage Vint, and a fourth drainelectrode D4 of the fourth transistor T4 is connected to the one end ofthe capacitor Cst and the first gate electrode G1 of the firsttransistor T1 through the third drain electrode D3 of the thirdtransistor T3. The fourth transistor T4 is turned on in response to thescan signal GIj applied thereto through the second scan line 152 andtransmits the initialization voltage Vint to the first gate electrode G1of the first transistor T1 to perform an initialization operation thatinitializes the voltage of the first gate electrode G1.

A fifth gate electrode G5 of the fifth transistor T5 is connected to thelight emitting control line 153, a fifth source electrode S5 of thefifth transistor T5 is connected to the first driving voltage line PL,and a fifth drain electrode D5 of the fifth transistor T5 is connectedto the first source electrode S1 of the first transistor T1 and thesecond drain electrode D2 of the second transistor T2.

A sixth gate electrode G6 of the sixth transistor T6 is connected to thelight emitting control line 153, a sixth source electrode S6 of thesixth transistor T6 is connected to the first drain electrode D1 of thefirst transistor T1 and the third source electrode S3 of the thirdtransistor T3, and a sixth drain electrode D6 of the sixth transistor T6is electrically connected to the anode of the light emitting diode ED.The fifth transistor T5 and the sixth transistor T6 are substantiallysimultaneously turned on in response to the light emitting controlsignal Ej applied thereto through the light emitting control line 153,and the first driving voltage ELVDD is compensated by the firsttransistor T1 connected to the diode and transmitted to the lightemitting diode ED.

A seventh gate electrode G7 of the seventh transistor T7 is connected tothe third scan line 154, a seventh source electrode S7 of the seventhtransistor T7 is connected to the sixth drain electrode D6 of the sixthtransistor T6 and the anode of the light emitting diode ED, and aseventh drain electrode D7 of the seventh transistor T7 is connected tothe initialization voltage line RL and the fourth source electrode S4 ofthe fourth transistor T4. According to another embodiment, the seventhgate electrode G7 of the seventh transistor T7 may be connected to thesecond scan line 152.

The one end of the capacitor Cst is connected to the first gateelectrode G1 of the first transistor T1 as described above, and theother end of the capacitor Cst is connected to the first driving voltageline PL. A cathode of the light emitting diode ED may be connected to aterminal that transmits the second driving voltage ELVSS. Theconfiguration of the pixel PXij according to the exemplary embodimentshould not be limited to that shown in FIG. 2, and the number of thetransistors, the number of the capacitors, which are included in thepixel PXij, and a connection relation of the transistors and thecapacitors may be changed in various ways.

The operation of the display device according to the exemplaryembodiment will be described with reference to FIGS. 2 and 3. In thefollowing descriptions, the first to seventh transistors T1 to T7 aredescribed as the p-channel type transistor, and the operationcorresponding to one frame period will be described.

Referring to FIGS. 2 and 3, the scan signals Sj−1, Sj, and Sj+1 having alow level may be sequentially applied to the first scan line 151connected to the pixel PXij as the scan signal GWj during one frameperiod.

The scan signal GIj having the low level is provided to the fourthtransistor T4 through the second scan line 152 during an initializationperiod. The scan signal GIj may be, for example, the (j−1)th scan signalSj−1. The fourth transistor T4 is turned on in response to the scansignal GIj having the low level, the initialization voltage Vint isapplied to the first gate electrode G1 of the first transistor T1through the fourth transistor T4, and the first transistor T1 isinitialized by the initialization voltage Vint.

Then, when the scan signal GWj having the low level is provided throughthe first scan line 151 during a data programming and compensationperiod, the second transistor T2 and the third transistor T3 are turnedon in response to the scan signal GWj having the low level. The scansignal GWj may be, for example, the j-th scan signal Sj. In this case,the first transistor T1 is connected in the diode configuration by theturned-on third transistor T3 and is forward biased. Accordingly, acompensation voltage Di-Vth obtained by decreasing the data signal Diprovided through the data line 171 by the threshold voltage Vth of thefirst transistor T1 is applied to the first gate electrode G1 of thefirst transistor T1. That is, a gate voltage applied to the first gateelectrode G1 of the first transistor T1 may be the compensation voltageDi-Vth.

The first driving voltage ELVDD and the compensation voltage Di-Vth areapplied to both ends of the capacitor Cst, and the capacitor Cst storeselectric charges corresponding to a difference in voltage between theboth ends of the capacitor Cst.

The seventh transistor T7 is turned on in response to the scan signalGBj having the low level, which is applied thereto through the thirdscan line 154, during a bypass period. The scan signal GBj may be the(j+1)th scan signal Sj+1. Due to the turned-on seventh transistor T7, aportion of the driving current Id may be discharged through the seventhtransistor T7 as a bypass current Ibp.

When the light emitting diode ED emits the light even in the case wherea minimum current of the driving transistor T1 displaying a black imageflows as a driving current, the black image is not appropriatelydisplayed. Therefore, the bypass transistor T7 of the organic lightemitting display device according to an exemplary embodiment maydisperse some of the minimum current of the driving transistor T1 as thebypass current Ibp to a current path other than a current path towardthe light emitting diode. Here, the minimum current of the drivingtransistor T1 indicates a current in a condition in which a gate-sourcevoltage Vgs of the driving transistor T1 is less than the thresholdvoltage Vth, such that the driving transistor T1 is turned off. Theminimum driving current (for example, a current of about 10 pA or less)in the condition in which the driving transistor T1 is turned off istransferred to the light emitting diode ED, such that an image having ablack brightness is displayed. In the case where the minimum drivingcurrent displaying the black image flows, an influence of a bypasstransfer of the bypass current Ibp is large. On the other hand, in thecase where a large driving current displaying an image such as a generalimage or a white image flows, an influence of the bypass current Ibp maybe hardly present. Therefore, in the case where the driving currentdisplaying the black image flows, a light emitting current Ted of thelight emitting diode ED decreased from the driving current Id by anamount of the bypass current Ibp exiting through the bypass transistorT7 has a minimum current amount, which is a level that may certainlydisplay the black image. Therefore, an accurate black brightness imageis implemented using the bypass transistor T7, thereby making itpossible to improve a contrast ratio. In the present exemplaryembodiment, the scan signal GBj that is bypass signal is the same as thenext scan signal Sj+1, but it should not be limited thereto or thereby.

Then, a level of the light emitting control signal Ej provided throughthe light emitting control line 153 is changed from a high level to alow level during a light emitting period. The fifth transistor T5 andthe sixth transistor T6 are turned on in response to the light emittingcontrol signal Ej during the light emitting period. Accordingly, thedriving current Id is generated due to the voltage difference betweenthe gate voltage of the first gate electrode G1 of the first transistorT1 and the first driving voltage ELVDD, the driving current Id issupplied to the light emitting diode ED through the sixth transistor T6,and thus the light emitting current Ied flows through the light emittingdiode ED. During the light emitting period, the gate-source voltage Vgsof the first transistor T1 is maintained in the following of‘(Di-Vth)-ELVDD’ by the capacitor Cst, and the driving current Id may bein proportion to ‘(Di-ELVDD)’ corresponding to a square of a valueobtained by subtracting the threshold voltage from the gate-sourcevoltage according to a current-voltage relationship of the firsttransistor T1. Accordingly, the driving current Id may be determined inregardless of the threshold voltage Vth of the first transistor T1.

Hereinafter, the structure of the pixel will be described in detail withreference to FIGS. 4 and 5. For the convenience of understanding, theplanar structure in the plan view of the pixel will be mainly described,and then the cross-sectional structure of the pixel will be described indetail.

FIG. 4 is a plan view showing one pixel of an organic light emittingdisplay device according to an exemplary embodiment of the presentdisclosure. FIG. 5 is a cross-sectional view taken along a line VI-VI′of FIG. 4 to show the organic light emitting display device.

The pixel PXij according to an embodiment may include a first conductivelayer including the first scan line 151 transmitting the scan signalGWj, the second scan line 152 transmitting the scan signal GIj, thethird scan line 154 transmitting the scan signal GBj, and the lightemitting control line 153 transmitting the light emitting control signalEj. The first conductive layer is located on one surface of thesubstrate 110. The substrate 110 may include an inorganic or organicinsulating material, such as glass, plastic, or the like, and may haveflexibility.

The scan lines 151, 152, and 154, the light emitting control line 153,and the third driving voltage line BMLj may extend in the same direction(e.g., the first direction DR1) when viewed in a plan view. The firstscan line 151 may be disposed between the second scan line 152 and thelight emitting control line 153 when viewed in a plan view.

The pixel PXij of the display device according to an exemplaryembodiment may further include a second conductive layer including acapacitor electrode CE and the initialization voltage line RL. Thesecond conductive layer is disposed on a different layer from the firstconductive layer when viewed in a cross section. For example, the secondconductive layer may be disposed above the first conductive layer whenviewed in a cross section.

The capacitor electrode CE and the initialization voltage line RL extendin substantially the same direction (e.g., the first direction DR1) asthe scan lines 151, 152, and 154 when viewed in a plan view.

The pixel PXij according to an embodiment may further include a thirdconductive layer including the data line 171 transmitting the datasignal Di and the first driving voltage line PL transmitting the firstdriving voltage ELVDD. The third conductive layer is disposed on adifferent layer from the first conductive layer and the secondconductive layer when viewed in a cross section. For example, the thirdconductive layer may be disposed above the second conductive layer, mayinclude the same material, and may be disposed on the same layer.

The data line 171 and the first driving voltage line PL may extend insubstantially the same direction (e.g., the second direction DR2) whenviewed in a plan view and may cross the scan lines 151, 152, and 154,the light emitting control line 153, the initialization voltage line RL,and the capacitor electrode CE.

The pixel PXij may include the first to seventh transistors T1 to T7 andthe capacitor Cst, which are connected to the scan lines 151, 152, and154, the light emitting control line 153, the data line 171, and thefirst driving voltage line PL, and the light emitting diode ED.

The channel of each of the first to seventh transistors T1 to T7 may beformed in one active pattern 105, and the active pattern 105 may be bentinto various shapes. The active pattern 105 may include a semiconductormaterial, such as polycrystalline silicon or oxide semiconductor. Theactive pattern 105 may be disposed between the substrate 110 and thefirst conductive layer when viewed in a cross section.

The active pattern 105 includes first to seventh active patterns A1 toA7 respectively corresponding to the first to seventh transistors T1 toT7. The first active pattern A1 includes a first source electrode S1, afirst channel C1, and a first drain electrode D1. The first sourceelectrode S1 is connected to the second drain electrode D2 of the secondtransistor T2 and the fifth drain electrode D5 of the fifth transistorT5, and the first drain electrode D1 is connected to the third sourceelectrode S3 of the third transistor 3 and the sixth source electrode S6of the sixth transistor T6.

The first active pattern A1 may include polycrystalline silicon or oxidesemiconductor. The oxide semiconductor may include one of an oxide basedon titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum(Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), or indium (In)and complex oxides thereof, such as zinc oxide (ZnO),indium-gallium-zinc oxide (In-Ga—Zn-O), indium-zinc oxide (Zn—In—O),zinc-tin oxide (Zn—Sn—O), indium-gallium oxide (In—Ga—O), indium-tinoxide (In—Sn—O), indium-zirconium oxide (In—Zr—O), indium-zirconium-zincoxide (In—Zr—Zn—O), indium-zirconium-tin oxide (In—Zr—Sn—O),indium-zirconium-gallium oxide (In—Zr—Ga—O), indium-aluminum oxide(In—Al—O), indium-zinc-aluminum oxide (In—Zn—Al—O), indium-tin-aluminumoxide (In—Sn—Al—O), indium-aluminum-gallium oxide (In—Al—Ga—O),indium-tantalum oxide (In—Ta—O), indium-tantalum-zinc oxide(In-Ta—Zn-O), indium-tantalum-tin oxide (In—Ta—Sn—O),indium-tantalum-gallium oxide (In—Ta—Ga—O), indium-germanium oxide(In—Ge—O), indium-germanium-zinc oxide (In—Ge—Zn—O),indium-germanium-tin oxide (In—Ge—Sn—O), indium-germanium-gallium oxide(In—Ge—Ga—O), titanium-indium-zinc oxide (Ti—In—Zn—O), andhafnium-indium-zinc oxide (Hf—In—Zn—O). In the case where the firstactive pattern A1 includes the oxide semiconductor, an additionalprotective layer may be added to protect the oxide semiconductor that isvulnerable to external environment, e.g., high temperature.

A first channel C1 of the first active pattern A1 may be channel-dopedwith an n-type impurity or a p-type impurity, and the first sourceelectrode S1 and the first drain electrode D1 may be spaced apart fromeach other such that the first channel C1 is disposed therebetween andmay be doped with a doping impurity opposite to the doping impurityprovided to the first channel C1.

The first gate electrode G1 is disposed above the first channel C1 ofthe first active pattern A1 and has an island shape. The first gateelectrode G1 is connected to the fourth drain electrode D4 of the fourthtransistor T4 and the third drain electrode D3 of the third transistorT3 by a gate bridge GB through a contact hole H1 and a contact hole H3.The first gate electrode G1 overlaps with the capacitor electrode CE,acts as the gate electrode of the first transistor T1, and acts as oneelectrode of the capacitor Cst. That is, the first gate electrode G1forms the capacitor Cst with the capacitor electrode CE.

The second transistor T2 is disposed above the substrate 110 andincludes a second active pattern A2 and the second gate electrode G2.The second active pattern A2 includes the second source electrode S2, asecond channel C2, and the second drain electrode D2. The second sourceelectrode S2 is connected to the data line 171 through a contact holeH2, and the second drain electrode D2 is connected to the first sourceelectrode S1 of the first transistor T1. The second channel C2 that is achannel area of the second active pattern A2 overlapped with the secondgate electrode G2 is disposed between the second source electrode S2 andthe second drain electrode D2. That is, the second active pattern A2 isconnected to the first active pattern A1.

The lower gate electrode BG2 is disposed between the second activepattern A2 and the substrate 110. The lower gate electrode BG2 isintegrally formed with the third driving voltage line BMLj. The secondchannel C2 of the second active pattern A2 overlaps with the thirddriving voltage line BMLj, the third driving voltage VGH is applied tothe third driving voltage line BMLj, and electric charges, such aselectrons or holes, are accumulated in the second channel C2 of thesecond active pattern A2 in accordance with a polarity of the powersource supplied to the third driving voltage line BMLj, therebycontrolling a threshold voltage of the second transistor T2.

That is, the threshold voltage of the second transistor T2 may decreaseor increase using the third driving voltage line BMLj, and a hysteresisphenomenon of the second transistor T2 may be improved by controllingthe threshold voltage of the second transistor T2.

In the present exemplary embodiment, the third driving voltage line BMLjis disposed under the first scan line 151. A width in the seconddirection DR2 of the third driving voltage line BMLj is wider than awidth in the second direction DR2 of the first scan line 151.

The second channel C2 of the second active pattern A2 may bechannel-doped with the n-type impurity or the p-type impurity, and thesecond source electrode S2 and the second drain electrode D2 may bespaced apart from each other such that the second channel C2 is disposedtherebetween and may be doped with a doping impurity opposite to thedoping impurity provided to the second channel C2. The second activepattern A2 is disposed on the same layer as the first active pattern A1,includes the same material as the first active pattern A1, and isintegrally formed with the first active pattern A1.

The second gate electrode G2 is disposed above the second channel C2 ofthe second active pattern A2 and is integrally formed with the firstscan line 151.

The lower gate electrode, i.e., the third driving voltage line BMLj isnot disposed between the first active pattern A1 and the substrate 110.In other words, the first channel C1 of the first active pattern A1 doesnot overlap with the third driving voltage line BMLj.

The third transistor T3 is disposed above the substrate 110 and includesa third active pattern A3 and the third gate electrode G3.

The third active pattern A3 includes the third source electrode S3, athird channel C3, and the third drain electrode D3. The third sourceelectrode S3 is connected to the first drain electrode D1, and the thirddrain electrode D3 is connected to the first gate electrode G1 of thefirst transistor T1 by a gate bridge GB provided in a contact hole H3.The third channel C3 that is a channel area of the third active patternA3 overlapped with the third gate electrode G3 is disposed between thethird source electrode S3 and the third drain electrode D3. That is, thethird active pattern A3 connects to the first active pattern A1 and thefirst gate electrode G1.

The third channel C3 of the third active pattern A3 may be channel-dopedwith the n-type impurity or the p-type impurity, and the third sourceelectrode S3 and the third drain electrode D3 may be spaced apart fromeach other such that the third channel C3 is disposed therebetween andmay be doped with a doping impurity opposite to the doping impurityprovided to the third channel C3. The third active pattern A3 isdisposed on the same layer as the first active pattern A1 and the secondactive pattern A2, includes the same material as the first activepattern A1 and the second active pattern A2, and is integrally formedwith the first active pattern A1 and the second active pattern A2. Thethird gate electrode G3 is disposed above the third channel C3 of thethird active pattern A3 and is integrally formed with the first scanline 151.

The fourth transistor T4 is disposed above the substrate 110 andincludes a fourth active pattern A4 and the fourth gate electrode G4.

The fourth active pattern A4 includes the fourth source electrode S4, afourth channel C4, and the fourth drain electrode D4. The fourth sourceelectrode S4 is connected to the initialization voltage line RL throughthe contact hole H4, and the fourth drain electrode D4 is connected tothe first gate electrode G1 of the first transistor T1 by the gatebridge GB through the contact hole H3. The fourth channel C4 that is achannel area of the fourth active pattern A4 overlapped with the fourthgate electrode G4 is disposed between the fourth source electrode S4 andthe fourth drain electrode D4. That is, the fourth active pattern A4connects to the initialization voltage line RL and the first gateelectrode G1 and is connected to the third active pattern A3 and thefirst gate electrode G1.

The fourth channel C4 of the fourth active pattern A4 may bechannel-doped with the n-type impurity or the p-type impurity, and thefourth source electrode S4 and the fourth drain electrode D4 may bespaced apart from each other such that the fourth channel C4 is disposedtherebetween and may be doped with a doping impurity opposite to thedoping impurity provided to the fourth channel C4. The fourth activepattern A4 is disposed on the same layer as the first active pattern A1,the second active pattern A2, and the third active pattern A3, includesthe same material as the first active pattern A1, the second activepattern A2, and the third active pattern A3, and is integrally formedwith the first active pattern A1, the second active pattern A2, and thethird active pattern A3. The fourth gate electrode G4 is disposed abovethe fourth channel C4 of the fourth active pattern A4 and is integrallyformed with the second scan line 152.

The fifth transistor T5 is disposed above the substrate 110 and includesa fifth active pattern A5 and the fifth gate electrode G5.

The fifth active pattern A5 includes the fifth source electrode S5, afifth channel C5, and the fifth drain electrode D5. The fifth sourceelectrode S5 is connected to the first driving voltage line PL through acontact hole H5, and the fifth drain electrode D5 is connected to thefirst source electrode S1 of the first transistor T1. The fifth channelC5 that is a channel area of the fifth active pattern A5 overlapped withthe fifth gate electrode G5 is disposed between the fifth sourceelectrode S5 and the fifth drain electrode D5. That is, the fifth activepattern A5 connects the first driving voltage line PL and the firstactive pattern A1.

The fifth channel C5 of the fifth active pattern A5 may be channel-dopedwith the n-type impurity or the p-type impurity, and the fifth sourceelectrode S5 and the fifth drain electrode D5 may be spaced apart fromeach other such that the fifth channel C5 is disposed therebetween andmay be doped with a doping impurity opposite to the doping impurityprovided to the fifth channel C5. The fifth active pattern A5 isdisposed on the same layer as the first active pattern A1, the secondactive pattern A2, the third active pattern A3, and the fourth activepattern A4, includes the same material as the first active pattern A1,the second active pattern A2, the third active pattern A3, and thefourth active pattern A4, and is integrally formed with the first activepattern A1, the second active pattern A2, the third active pattern A3,and the fourth active pattern A4.

The fifth gate electrode G5 is disposed above the fifth channel C5 ofthe fifth active pattern A5 and is integrally formed with the lightemitting control line 153.

The sixth transistor T6 is disposed above the substrate 110 and includesa sixth active pattern A6 and the sixth gate electrode G6.

The sixth active pattern A6 includes the sixth source electrode S6, asixth channel C6, and the sixth drain electrode D6. The sixth sourceelectrode S6 is connected to the first drain electrode D1 of the firsttransistor T1, and the sixth drain electrode D6 is connected to thefirst electrode E1 of the light emitting diode ED through a contact holeH6. The sixth channel C6 that is a channel area of the sixth activepattern A6 overlapped with the sixth gate electrode G6 is disposedbetween the sixth source electrode S6 and the sixth drain electrode D6.That is, the sixth active pattern A6 connects the first active patternA1 and the first electrode E1 of the light emitting diode ED.

The sixth channel C6 of the sixth active pattern A6 may be channel-dopedwith the n-type impurity or the p-type impurity, and the sixth sourceelectrode S6 and the sixth drain electrode D6 may be spaced apart fromeach other such that the sixth channel C6 is disposed therebetween andmay be doped with a doping impurity opposite to the doping impurityprovided to the sixth channel C6. The sixth active pattern A6 isdisposed on the same layer as the first active pattern A1, the secondactive pattern A2, the third active pattern A3, the fourth activepattern A4, and the fifth active pattern A5, includes the same materialas the first active pattern A1, the second active pattern A2, the thirdactive pattern A3, the fourth active pattern A4, and the fifth activepattern A5, and is integrally formed with the first active pattern A1,the second active pattern A2, the third active pattern A3, the fourthactive pattern A4, and the fifth active pattern A5.

The sixth gate electrode G6 is disposed above the sixth channel C6 ofthe sixth active pattern A6 and is integrally formed with the lightemitting control line 153.

The seventh transistor T7 is disposed above the substrate 110 andincludes a seventh active pattern A7 and the seventh gate electrode G7.

The seventh active pattern A7 includes the seventh source electrode S7,a seventh channel C7, and the seventh drain electrode D7. The seventhsource electrode S7 is connected to a first electrode of an organiclight emitting element ED, and the seventh drain electrode D7 isconnected to the fourth source electrode S4 of the fourth transistor T4.The seventh channel C7 that is a channel area of the seventh activepattern A7 overlapped with the seventh gate electrode G7 is disposedbetween the seventh source electrode S7 and the seventh drain electrodeD7. That is, the seventh active pattern A7 connects the first electrodeof the organic light emitting element and the fourth active pattern A4.

The seventh channel C7 of the seventh active pattern A7 may bechannel-doped with the n-type impurity or the p-type impurity, and theseventh source electrode S7 and the seventh drain electrode D7 may bespaced apart from each other such that the seventh channel C7 isdisposed therebetween and may be doped with a doping impurity oppositeto the doping impurity provided to the seventh channel C7. The seventhactive pattern A7 is disposed on the same layer as the first activepattern A1, the second active pattern A2, the third active pattern A3,the fourth active pattern A4, the fifth active pattern A5, and the sixthactive pattern A6, includes the same material as the first activepattern A1, the second active pattern A2, the third active pattern A3,the fourth active pattern A4, the fifth active pattern A5, and the sixthactive pattern A6, and is integrally formed with the first activepattern A1, the second active pattern A2, the third active pattern A3,the fourth active pattern A4, the fifth active pattern A5, and the sixthactive pattern A6.

The seventh gate electrode G7 is disposed above the seventh channel C7of the seventh active pattern A7 and is integrally formed with the thirdscan line 154.

As described above, the lower gate electrode BG2 integrally formed withthe third driving voltage line BMLj is disposed between the secondactive pattern A2 of the second transistor T2 and the substrate 110, butthe lower gate electrode BG2, i.e., the third driving voltage line BMLjis not disposed between the substrate 110 and the active patterns A1,A3, A4, A5, A6, and A7 of the first, third, fourth, fifth, sixth, andseventh transistors T1, T3, T4, T5, T6, and T7.

The capacitor Cst includes the one electrode and the other electrode,which face each other such that the insulating layer is disposed betweenthe electrodes. The one electrode may be the capacitor electrode CE, andthe other electrode may be the first gate electrode G1. The capacitorelectrode CE is disposed above the first gate electrode G1 and connectedto the first driving voltage line PL through the contact hole H7. Thecapacitor electrode CE and the first gate electrode G1 may be formed ofthe same or different metal materials on different layers from eachother.

The capacitor electrode CE includes an opening OA overlapped with aportion of the first gate electrode G1, and the gate bridge GB isconnected to the first gate electrode G1 through the opening OA.

The gate bridge GB is disposed on the first scan line 151, spaced apartfrom the first driving voltage line PL, is connected to the third drainelectrode D3 of the third active pattern A3 and the fourth drainelectrode D4 of the fourth active pattern A4 through the contact holeH3, and is connected to the first gate electrode G1 through the contacthole H1 formed through the opening OA of the capacitor electrode CE.

The initialization voltage line RL is connected to the fourth sourceelectrode S4 of the fourth active pattern A4 through the contact holeH4. The initialization voltage line RL is disposed on the same layer asand includes as the same material as the first electrode E1 of the lightemitting diode ED. Meanwhile, the initialization voltage line RL may bedisposed on a different layer from and may include a different materialfrom the first electrode E1 according to another embodiment of thepresent disclosure.

The structure of the display device according to the exemplaryembodiment in the cross section will be described in detail withreference to FIG. 5.

A buffer layer 120 may be disposed on the substrate 110. The bufferlayer 120 prevents impurities from being transferred to an upper layerof the buffer layer 120 from the substrate 110, particularly, to theactive pattern 105 to improve characteristics of the active pattern 105and relieve stress. The buffer layer 120 may include an inorganicinsulating material and/or an organic insulating material, such assilicon nitride (SiNx) or silicon oxide (SiOx). At least a portion ofthe buffer layer 120 may be omitted.

The lower gate electrode BG2 as described above is disposed on thebuffer layer 120, and the first insulating layer 130 is disposed on thelower gate electrode BG2. The lower gate electrode BG2 includes themetal material, however it should not be limited to the metal material.That is, the lower gate electrode BG2 may include other materials thatmay be used to supply the power, e.g., a conductive polymer. The activepattern 105 is disposed on the first insulating layer 130, and thesecond insulating layer 140 is disposed on the active pattern 105.

The above-mentioned first conductive layer may be disposed on the firstinsulating layer 130. The first conductive layer may include copper(Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), or alloys thereof.

A third insulating layer 150 may be disposed on the first conductivelayer and the second insulating layer 140.

The above-mentioned second conductive layer may be disposed on the thirdinsulating layer. The second conductive layer may include copper (Cu),aluminum (Al), molybdenum (Mo), titanium (Ti), or alloys thereof.

A fourth insulating layer 160 may be disposed on the second conductivelayer and the third insulating layer 150.

At least one of the first insulating layer 130, the second insulatinglayer 140, the third insulating layer 150, and the fourth insulatinglayer 160 may include an inorganic insulating material and/or an organicinsulating material, such as silicon nitride (SiNx), silicon oxide(SiOx), or silicon oxynitride (SiOxNy).

The first insulating layer 130, the second insulating layer 140, thethird insulating layer 150, and the fourth insulating layer 160 mayinclude the contact H1 disposed above the first gate electrode G1, thecontact hole H2 disposed above the second source electrode S2 of thesecond transistor T2, the contact hole H3 disposed above the third drainelectrode D3 of the third transistor T3 and the fourth drain electrodeD4 of the fourth transistor T4, the contact hole H4 disposed above theinitialization voltage line RL, the contact hole H5 disposed above thefifth source electrode S5 of the fifth transistor T5, the contact holeH6 disposed above the sixth drain electrode D6 of the sixth transistorT6, and the contact hole H7 disposed above the capacitor electrode CE.

The above-mentioned third conductive layer may be disposed on the fourthinsulating layer 160. The third conductive layer may include copper(Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), or alloys thereof.

The capacitor electrode CE is disposed to overlap with the first gateelectrode G1, and the third insulating layer 150 is disposed between thecapacitor electrode CE and the first gate electrode G1, thereby formingthe capacitor Cst.

A protective layer 180 is disposed on the third conductive layer and thefourth insulating layer 160. The protective layer 180 may include anorganic insulating material, such as a polyacryl-based resin or apolyimide-based resin, and an upper surface of the protective layer 180may be flat.

The fourth conductive layer including the first electrode E1 may bedisposed on the protective layer 180. The fourth conductive layer mayinclude copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), oralloys thereof. A pixel definition layer 190 may be disposed on theprotective layer 180 and the fourth conductive layer. The pixeldefinition layer 190 is provided with an opening 191 definedtherethrough above the pixel electrode E1.

An organic light emitting layer OL is disposed on the pixel electrodeE1. The organic light emitting layer OL may be disposed in the opening191. The organic light emitting layer OL may include an organic lightemitting material or an inorganic light emitting material.

A second electrode E2 is disposed on the organic light emitting layerOL. The second electrode E2 may be formed on the pixel definition layer190 and may extend over the plural pixels.

The first electrode E1, the organic light emitting layer OL, and thesecond electrode E2 form the light emitting diode ED.

An encapsulation layer (not shown) may further disposed on the secondelectrode E2 to protect the light emitting diode ED. The encapsulationlayer may include an inorganic layer and an organic layer which arealternately stacked one on another.

The first electrode E1 is connected to the sixth drain electrode D6 ofthe sixth transistor T6 through a contact hole. The organic lightemitting layer OL is disposed between the first electrode E1 and thesecond electrode E2. The second electrode E2 is disposed on the organiclight emitting layer OL. At least one of the first electrode E1 and thesecond electrode E2 may be at least one of a light transmissiveelectrode, a light reflective electrode, and a light transflectiveelectrode, and a light emitted from the organic light emitting layer OLmay be emitted toward one or more of the first electrode E1 and thesecond electrode E2.

A capping layer may be disposed on the light emitting diode ED to coverthe light emitting diode ED, and a thin film encapsulation layer or anencapsulation substrate may be disposed above the light emitting diodeED such that the capping layer is disposed therebetween.

FIG. 6 is a view showing a variation of the threshold voltage of thesecond transistor shown in FIG. 2.

Referring to FIGS. 2 and 6, the threshold voltage of the secondtransistor T2 is positively shifted when an ambient temperature ischanged from a room temperature to a high temperature (e.g., about 70Celsius degrees). That is, a threshold voltage curve HT in the hightemperature is more shifted to a positive direction (+ direction) than athreshold voltage curve LT in the room temperature. In the case wherethe threshold voltage of the second transistor T2 is positively shifted,a leakage current flowing through the second transistor T2 and the thirdtransistor T3 may increase during the light emitting period in which thesecond transistor T2 and the third transistor T3 are required tomaintain an off state. The leakage current flowing through the secondtransistor T2 and the third transistor T3 increases a voltage level ofthe first gate electrode G1 of the first transistor T1 and decreases thedriving current Id supplied to the light emitting diode ED. As a result,a light emission brightness of the light emitting diode ED may bedeteriorated.

The second transistor T2 according to the exemplary embodiment of thepresent disclosure includes the lower gate electrode BG2, and the thirddriving voltage VGH is applied to the lower gate electrode BG2 throughthe third driving voltage line BMLj. The third driving voltage VGH maybe, for example, about 7 volts. For instance, when the third drivingvoltage VGH is about 7 volts, the threshold voltage of the secondtransistor T2 may be shifted by about −0.3 volts.

Accordingly, the light emission brightness of the light emitting diodeED may be prevented from being deteriorated by the positive shift of thethreshold voltage of the light emitting diode ED.

FIG. 7 is a plan view showing an AR1 area of the organic light emittingdisplay device shown in FIG. 1. FIG. 8 is a cross-sectional view takenalong a line VII-VII′ of FIG. 7.

Referring to FIGS. 1, 7, and 8, the voltage line 510 transmitting thethird driving voltage VGH from the voltage generator 500 extends in thesecond direction DR2. The light emitting lines EL1 to ELn and the scanlines SL1 to SLn extend in the first direction DR1 crossing the seconddirection DR2.

Each of the third driving voltage lines BML1 to BMLn may be arrangedparallel to a corresponding scan line among the scan lines SL1 to SLn.In the present exemplary embodiment, each of the third driving voltagelines BML1 to BMLn is arranged under a corresponding scan line among thescan lines SL1 to SLn. In addition, the number of the third drivingvoltage lines BML1 to BMLn is equal to the number of the pixels arrangedin the second direction DR2, i.e., the number of the scan lines SL1 toSLn.

The voltage line 510 is connected to the third driving voltage linesBML1 to BMLn through contact holes CH1 to CHn.

Referring to FIGS. 5, 7, and 8, the light emitting lines EL1 to ELn mayinclude the same material as and may be disposed on the same layer asthe light emitting control line 153. The voltage line 510 may bedisposed in the second conductive layer including the capacitorelectrode CE and the initialization voltage line RL. According toanother embodiment, the voltage line 510 may be disposed in the thirdconductive layer including the data line 171 and the first drivingvoltage line PL transmitting the first driving voltage ELVDD.

FIGS. 9A to 9F are cross-sectional views taken along lines VIII-VIII′and IX-IX′ of FIG. 4.

Referring to FIG. 9A, the buffer layer 120 is formed on the substrate110. The lower gate electrode BG2 is formed on the buffer layer 120. Thefirst insulating layer 130 and an initial semiconductor pattern SP1 areformed on the lower gate electrode BG2. The initial semiconductorpattern SP1 may be formed by depositing a semiconductor material andpatterning the semiconductor material. The initial semiconductor patternSP1 may be formed by further performing a crystallization process, suchas a heat treatment process.

Then, as shown in FIG. 9B, a photoresist PR is uniformly coated on theinitial semiconductor pattern SP1, and an area corresponding to thesecond active pattern A2 of the initial semiconductor pattern SP1 isdoped with a first impurity DM1. As an example, the first impurity DM1is a boron (B) ion.

Then, as shown in FIG. 9C, the photoresist PR is remove. The areacorresponding to the second active pattern A2 of the second transistorT2 of the initial semiconductor pattern SP1 is doped with the boron ion.The first impurity DM1 may be injected into the initial semiconductorpattern SP1 by a diffusion process or an ion injection process, howeverit should not be particularly limited.

Then, as shown in FIG. 9D, the second insulating layer 140 and the firstconductive layer CL1 are formed. The second insulating layer 140 may beformed by depositing, coating or printing an inorganic material and/oran organic material on the base substrate 110 or the buffer layer 120.The second insulating layer 140 may cover the initial semiconductorpattern SP1. Then, a conductive material is deposited on the secondinsulating layer 140 to form the first conductive layer CL1.

As shown in FIG. 9E, the second active pattern A2 and the fifth activepattern A5 are formed after forming the second gate electrode G2 and thefifth gate electrode G5. The second gate electrode G2 and the fifth gateelectrode G5 may be formed by patterning the first conductive layer CL1.The second gate electrode G2 and the fifth gate electrode G5 may besubstantially simultaneously patterned using the same mask. Meanwhile,this is merely exemplary, and the second gate electrode G2 and the fifthgate electrode G5 may be separately patterned using different masks fromeach other.

Then, a second impurity DM2 is injected into the initializationsemiconductor pattern SP1 to form the second active pattern A2 and thefifth active pattern A5. The second impurity DM2 may be injected intothe initialization semiconductor pattern SP1 using a diffusion processor an ion injection process, however it should not be particularlylimited.

The second impurity DM2 may include various materials. For example, thesecond impurity DM2 may include a trivalent element. In this case, thesecond active pattern A2 and the fifth active pattern A5 may be formed ap-type semiconductor.

The second impurity DM2 is injected into an area of the initializationsemiconductor pattern SP1, which is not overlapped with the second gateelectrode G2 and the fifth gate electrode G5, and thus theinitialization semiconductor pattern SP1 is formed in the second activepattern A2 including the second source electrode S2, the second channelC2, and the second drain electrode D2 and the fifth active pattern A5including the fifth source electrode S5, the fifth channel C5, and thefifth drain D5.

Accordingly, the second impurity DM2 having a relatively higherconcentration than that in the second channel C2 of the second activepattern A2 and the fifth channel C5 of the fifth active pattern A5exists in the second source electrode S2 and the second drain electrodeD2 of the second active pattern A2 and the fifth source electrode S5 andthe fifth drain electrode D5 of the fifth active pattern A5. That is,when the initialization semiconductor pattern SP1 is doped with ionimpurity using the second gate electrode G2 and the fifth gate electrodeG5 as a self-aligned mask, the initialization semiconductor pattern SP1includes the second active pattern A2 and the fifth active pattern A5,which are doped with the ion impurity.

Then, as shown in FIG. 9F, the third insulating layer 150, the fourthinsulating layer 160, the third conductive layer 171, the protectivelayer 180, the pixel definition layer 190, and the pixel electrode E1are sequentially stacked. In the present exemplary embodiment, the thirdconductive layer 171 is the data line.

In the case where the third driving voltage VGH (e.g., about 7 volts) isapplied to the lower gate electrode BG2 of the second transistor T2, thethreshold voltage of the second transistor T2 is negatively shifted. Ina case where the threshold voltage of the second transistor T2 isnegatively shifted more than a desired voltage, the concentration of thefirst impurity DM1 doped in the area corresponding to the second activepattern A2 of the initialization semiconductor pattern SP1 may bechanged.

For example, when the concentration of the boron (B) ion doped in thearea corresponding to the second active pattern A2 of the initializationsemiconductor pattern SP1 increases by about 1×10¹¹ atoms/cm², thethreshold voltage of the second transistor T2 is positive shifted byabout 0.1 volts.

That is, as the voltage level of the third driving voltage VGH appliedto the lower gate electrode BG2 of the second transistor T2 increases,the threshold voltage of the second transistor T2 is negatively shifted,and as the concentration of the boron (B) ion doped in the areacorresponding to the second active pattern A2 of the initializationsemiconductor pattern SP1 increases, the threshold voltage of the secondtransistor T2 is positively shifted. Accordingly, a range of thethreshold voltage of the second transistor T2 may be adjusted bycontrolling the voltage level of the third driving voltage VGH appliedto the lower gate electrode BG2 of the second transistor T2 and theconcentration of the boron (B) ion doped in the area corresponding tothe second active pattern A2 of the initialization semiconductor patternSP1.

According to another embodiment, the first impurity DM1 doped in thearea corresponding to the second active pattern A2 of the initializationsemiconductor pattern SP1 may be phosphorus (P) ion. As theconcentration of the phosphorus (P) ion doped in the area correspondingto the second active pattern A2 of the initialization semiconductorpattern SP1 increases, the threshold voltage of the second transistor T2is negatively shifted. That is, in a case where an amount of thenegative shift of the threshold voltage of the second transistor isinsufficient due to the third driving voltage VGH applied to the lowergate electrode BG2 of the second transistor T2, the concentration of thephosphorus (P) ion doped in the area corresponding to the second activepattern A2 of the initialization semiconductor pattern SP1 may increase.

FIG. 10 is a plan view showing an organic light emitting display deviceaccording to another exemplary embodiment of the present disclosure.

Referring to FIG. 10, an organic light emitting display device 600includes a display substrate 610 including a display area DPA and anon-display area NDA. A plurality of pixels (not shown) is arranged inthe display area DPA. A scan driving circuit 630 and a data drivingcircuit 400 are arranged in the non-display area NDA. A pad part 605including a plurality of pads P1 to Pk aligned along an edge of thenon-display area NDA is arranged in the noon display area NDA. The padsP1 to Pk are connected to an external host device (not shown) andreceive signals from the host device. One pad Pk among the pads P1 to Pkmay be a pad used to receive the third driving voltage VGH.

The scan driving circuit 300 generates a plurality of scan signals andsequentially outputs the scan signals to a plurality of scan lines SL1to SLn. In addition, the scan driving circuit 300 generates a pluralityof light emitting control signals and outputs the light emitting controlsignals to a plurality of light emitting lines EL1 to ELn.

The data driving circuit 400 outputs data signals to a plurality of datalines DL1 to DLm described later.

The display substrate 610 includes the scan lines SL1 to SLn, the lightemitting lines EL1 to ELn, the data lines DL1 to DLn, third drivingvoltage lines BML1 to BMLm, and pixels (not shown). The scan lines SL1to SLn extend in a first direction DR1. Each of the light emitting linesEL1 to ELn may be arranged parallel to a corresponding scan line amongthe scan lines SL1 to SLn. The data lines DL1 to DLm extend in a seconddirection DR2. The data lines DL1 to DLm are insulated from the scanlines SL1 to SLn and the light emitting lines EL1 to ELn while crossingthe scan lines SL1 to SLn and the light emitting lines EL1 to ELn.

Each of the third driving voltage lines BML1 to BMLj may be arrangedparallel to a corresponding data line among the data lines DL1 to DLm.In the present exemplary embodiment, the number of the third drivingvoltage lines BML1 to BMLm is equal to the number of the pixels arrangedin the first direction DR1, i.e., the number of the data lines DL1 toDLm. The third driving voltage lines BML1 to BMLm are insulated from thescan lines SL1 to SLn and the light emitting lines EL1 to ELn whilecrossing the scan lines SL1 to SLn and the light emitting lines EL1 toELn.

FIG. 11 is a plan view showing one pixel of an organic light emittingdisplay device according to an exemplary embodiment of the presentdisclosure. FIG. 12 is a cross-sectional view taken along a line X-X′ ofFIG. 11 to show the organic light emitting display device.

In FIGS. 11 and 12, the same elements of the pixel PXij are assignedwith the same reference numerals as the pixel PXij shown in FIGS. 4 and5.

Referring to FIG. 11, a third driving voltage line BMLi overlaps with adata line 171. When a third driving voltage VGH is applied to the thirddriving voltage line BMLi, a threshold voltage of a second transistor T2is controlled in accordance with the voltage level of the voltageapplied to the third driving voltage line BMLi.

In the present exemplary embodiment, the third driving voltage line BMLiis disposed under the data line 171. A width in the first direction DR1of the third driving voltage line BMLi is wider than a width in thefirst direction DR1 of the data line 171.

The cross-sectional structure of the display device according to anexemplary embodiment will be described in detail with reference to FIG.12.

A buffer layer 120 is disposed on a substrate 110. A lower gateelectrode BG2 is disposed on the buffer layer 120, and a firstinsulating layer 130 is disposed on the lower gate electrode BG2. Thelower gate electrode BG2 includes a metal material, however it shouldnot be limited to the metal material. That is, the lower gate electrodeBG2 may include other materials that may be used to supply the power,e.g., a conductive polymer. A second channel of a second active panel A2overlaps with the lower gate electrode BG2. When the third drivingvoltage VGH is applied to the lower gate electrode BG2, electriccharges, such as electrons or holes, are accumulated in the secondchannel C2 of the second active pattern A2 in accordance with a polarityof the power source applied to the third driving voltage line BMLi.Accordingly, the threshold voltage of the second transistor T2 iscontrolled.

Although the exemplary embodiments of the present inventive concept havebeen described, it is understood that the present inventive conceptshould not be limited to these exemplary embodiments but various changesand modifications can be made by one ordinary skilled in the art withinthe spirit and scope of the present inventive concept as hereinafterclaimed.

What is claimed is:
 1. An organic light emitting display devicecomprising: a substrate comprising a display area and a non-displayarea; a light emitting diode disposed on the substrate and overlappedwith the display area; a transistor comprising a gate electrode, achannel overlapped with the gate electrode when viewed in a plan view,and a lower electrode; and a voltage line disposed on the non-displayarea, wherein the lower electrode of the transistor overlaps with thegate electrode when viewed in a plan view with the channel interposedbetween the gate electrode and the lower electrode, and the lowerelectrode is electrically connected to the voltage line.
 2. The organiclight emitting display device of claim 1, wherein the lower electrode isdisposed between the substrate and an active pattern comprising thechannel of the transistor.
 3. The organic light emitting display deviceof claim 1, further comprising a scan line extending in a firstdirection, wherein the gate electrode of the transistor is electricallyconnected to the scan line.
 4. The organic light emitting display deviceof claim 3, further comprising data line extending in a second directiondifferent from the first direction, wherein the channel of thetransistor is electrically connected to the data line.
 5. The organiclight emitting display device of claim 4, wherein the voltage lineextending in the second direction in the non-display area.
 6. Theorganic light emitting display device of claim 1, further comprising adriving voltage line electrically connected to the voltage line.
 7. Theorganic light emitting display device of claim 6, wherein the drivingvoltage line extending in a first direction in the display area.
 8. Theorganic light emitting display device of claim 6, wherein the drivingvoltage line electrically connected to the voltage line through acontact hole, wherein the contact hole disposed on the non-display area.9. The organic light emitting display device of claim 1, wherein adriving voltage is provided to the lower electrode thorough the voltageline, and wherein a voltage level of the driving voltage iscorresponding to a high voltage of a scan signal.
 10. An organic lightemitting display device comprising: a substrate comprising a displayarea and a non-display area; a pixel disposed on the substrate; a scanline extending in a first direction and connected to the pixel; and adata line extending in a second direction crossing the first directionand connected to the pixel, wherein the pixel comprising: a lightemitting diode disposed on the display area; and a transistor comprisinga gate electrode, a channel overlapped with the gate electrode whenviewed in a plan view, and a lower electrode overlapped with the gateelectrode when viewed in a plan view, wherein the channel interposedbetween the gate electrode and the lower electrode, wherein the lowerelectrode is electrically connected to the scan line.
 11. The organiclight emitting display device of claim 10, wherein the scan linetransmits a scan signal which swings between a high voltage and a lowvoltage.
 12. The organic light emitting display device of claim 10,wherein the lower electrode receives a scan signal transmitted to thescan line.
 13. The organic light emitting display device of claim 10,further comprising a voltage line disposed on the non-display area. 14.The organic light emitting display device of claim 13, wherein thevoltage line electrically connected to the lower electrode through acontact hole, and wherein the contact hole disposed on the non-displayarea.